1. Field of the Invention
This invention relates generally to data processing system architectures, and more specifically to an apparatus for intersystem I/O channel paging.
2. Description of the Prior Art
Various approaches have been employed to provide data communications between I/O processors and computer system multiprocessor networks. For example, one prior art approach to multiprocessor data communications architecture uses a shared bus configuration. The shared bus is often employed in conjunction with shared memory, control block conventions, ID's, and/or locks to provide orderly communications and data integrity. However, this approach does not provide a comprehensive system I/O channel mechanism.
Various data communications architectures have been developed in the field of telephone station signalling. One such system uses databit encoding protocols as message sets, which are then conveyed within the structure of existing communications line protocols. However, it should be noted that systems which provide for data communications over standard telephone lines are not generally adaptable in the context of a multiprocessor-I/O device operational environment. These telephonic communications systems lack the data structures and hardware which are required to implement communications between a plurality of I/O devices and various multiprocessors.
Data processing system architectures have been developed which include a central processing unit (CPU), and a plurality of independent I/O processors. The I/O processors are connected in parallel through a bus to provide access to a common working memory. The I/O processors access specified areas of the working memory under the control of a memory access control unit. A set of tridirectional gates connects the working memory to the CPU and to the I/O processors. These systems use a mailbox function to send messages between the CPU and the I/O processors. When the CPU sends instructions to a particular I/O processor, the appropriate message is loaded into an electronic mailbox by means of memory read operations. This system provides for the transfer of relatively basic message structures which include a channel number corresponding to a given I/O processor, and a function code corresponding to a particular operation.
Communications mechanisms for use in multiprocessor systems often operate in the context of a single, shared memory. For example, a commonly-utilized technique involves the sharing and allocation of main memory cycles accessed by I/O devices. These systems may employ a data structure known as a local communications segment. Each communications segment is associated with a specific processor, and the segment is stored in memory. The segment is used for processor-specific communications. Each segment contains a field allocated to control flags. The control flags are set by one processor and later inspected by the same and/or other processors. Based upon the state of the control flag, one or more functions or operational sequences may be performed.
Processor controlled digital communications devices may be employed to accept message commands from a communications system as part of a communications system protocol. These message commands are stripped from the protocol and then combined within the communications device to control signaling sequences at the communications device. Multibit time-separated information fields are used in conjunction with a single bit signaling field. The signaling field bits are compiled over several frames to form various command messages. However, these prior-art digital communications devices are not capable of initiating I/O instructions and actions.
Another commonly-utilized approach to I/O channel communications employs a task handler to initiate and coordinate I/O instructions and actions. Although a few of these task handler systems offer a function called "Send Message", this function serves the limited purpose of enqueueing a task to be executed. These prior-art "Send Message" functions are not capable of initiating I/O instructions and actions.
What is needed is an improved I/O channel system capable of initiating I/O instructions and actions. The approach should provide a comprehensive system I/O channel mechanism which is not dependent upon the use of a shared data bus. The system should include sufficient hardware and data structures to enable operation in the context of a network comprised of I/O devices and one or more multiprocessors.